The invention relates to a reconfigurable field effect transistor (RFET) comprising a nanowire, wherein the nanowire comprises two Schottky contacts and two gate contacts partially enclosing the nanowire along the outer periphery thereof.
The invention moreover relates to a nanowire-parts-array as well as to an integrated circuit which comprises the reconfigurable field effect transistors according to the invention.
To date, according to MOORE's law, the scaling of highly integrated circuits has halved the surface of the conventional components approximately every two years, and thus the number of components and the associated functionality of a circuit have doubled. However, conventional scaling of silicon-based planar CMOS field effect transistors (CMOSFETs) has reached the physical limits. The transition to three-dimensional multigate structures (FinFETs) first of all ensures further scaling of the components and thus preserves MOORE's law. However, these FinFETs too cannot be made as small as desired and will reach their physical limits in the foreseeable future. Therefore, alternative approaches to increasing the integration and functionality in comparison to conventional scaling are urgently needed.
A possible alternative consists of the functional enhancement of circuit elements. Here, multifunctional devices with adaptable logic and computation blocks can be used, by means of which an increase in functionality can be ensured even beyond the end of conventional scaling according to MOORE.
However, the conventional CMOS circuits consisting of n-MOSFETs (electron-conducting) and p-MOSFETs (hole-conducting) are less suitable for this purpose, since the polarity of their transistors is predetermined by the production process thereof and the implanted resulting dopants used in the process are firmly fixed, and thus the circuit can no longer be changed subsequently.
However, the increase in functionality is known from horizontal reconfigurable field effect transistors (RFET). The reconfigurable field effect transistors are based on silicon nanowires lying horizontally on a substrate, with separately gated Schottky barriers. The term Schottky barriers is used to denote the boundary surface between a metal and a semiconductor. Here, in a simplified consideration, it can be assumed that a metal and a semiconductor can be assembled without any change in the electron structure due to the metal-semiconductor bonding in the solid made of metal and semiconductor. If one assumes that the work function of the metal q*φm is greater than the electron affinity of the semiconductor q*χ—a condition which is satisfied in most metal-semiconductor combinations—, then, on the boundary surface between the Fermi edge WF of the metal and the lower conduction band edge WL of the semiconductor, a potential step forms having a height φB=φm−χ that depends on the material combination. The Fermi energy WF of the undisturbed (for example, n-doped) semiconductor is just below the conduction band (except in degenerate semiconductors). In the case of contact between metal and semiconductor, charge compensation occurs, the Fermi energies of metal and semiconductor material converge, and, subsequently, there is only one common Fermi energy in the thermodynamic equilibrium. Due to the different work functions of the two materials, there is a charge effect on the two surfaces. On the metal surface, the “−” electrons accumulate, which flow out of the semiconductor surface and thus generate “+” positive interfering sites in the semiconductor. A potential wall and a “bending” of the bands of the semiconductor occur. Via band bending, the electrons are able to leave the semiconductor, and a so-called depletion zone W0 forms, in which the potential energy of the electrons in the conduction band (majority charge carrier) is high. As explained, the electrons in the semiconductor have a higher energy state than the electrons in the metal. If positive voltage is then applied (negative pole on the n-type semiconductor), electrons are pushed from the semiconductor material into the depletion zone and the potential barrier becomes smaller. Electrons can then flow from the semiconductor into the metal (“forward direction,” English forward bias). On the other hand, if one applies a negative voltage (which is not sufficiently large for a breakthrough to occur), the electrons are pulled even more strongly in direction of the metal, and the thickness of the depletion zone (“barring direction,” English reverse bias) increases. Only a very low current occurs, because a few electrons of the metal can overcome the barrier due to thermal excitation, or “tunnel” through the barrier (quantum mechanical tunnel effect). The diagrammatic representations of a Schottky barrier and of a RFET are represented in FIGS. 1 and 2. Here, WV is the energy level of the valency band, WL is the lower energy edge of the conduction band, φsc is the work function of the semiconductor, q is the electrical charge, and Vi is the energy of the vacuum level.
In the case of the RFET, the source and drain contacts are each formed by a Schottky barrier, wherein a gate potential is used for the purpose of injecting the predominant charge carriers directly into the valency or conduction band at the site of band bending. FIG. 2 shows the electron density of a nanowire FET in the conductive state, wherein the transistor structure is represented cut in half along the longitudinal extent thereof.
In the case of silicon nanowires, the formation of a sharp, i.e., abrupt metal-semiconductor boundary surface can be implemented. In contrast to bulk materials, due to the small dimensions of the nanowires, the electrostatic control of the active areas (metal-semiconductor transitions) can occur substantially more simply and efficiently.
Three different reconfigurable designs for nanowire FETs are known, which depend on the control of the charge carrier selection and the charge carrier concentration:                A) Selective charge carrier injection and concentration control on the contacts;        B) Selection of the polarity on the contacts, and control of the charge concentration in the channel;        C) Ambipolar operation with charge carrier filtering in the channel. The designs are represented diagrammatically in FIG. 3a) to c).        
In case A), the selective charge carrier injection and the control of the charge carrier concentration occur directly on the source and drain contacts 3 of RFET 1. For this purpose, the Schottky barriers are gated independently of one another at the source and drain transitions 3, and no gate contact is necessary in the center of the channel. On the drain contact side, a gate contact can block the undesired charge carriers from entering into the channel, as a result of which the polarity of the RFET is programmed. On the source contact side, the other gate contact is used for setting the conductivity of the other charge carrier type (control of the RFET) (FIG. 3a)
In case B), the two Schottky transitions 6 are controlled at the same time, wherein either holes (Vg<0) or electrons (Vg>0) are accumulated in the channel, and thus the polarity of the RFET is programmed. Using an additional gate contact 42 in the center of the channel 5, the flow of the charge carriers from source contact to drain contact 3 can be set (controlled) (FIG. 3b).
In case C), the same structure as in case B) is used, except that the gate contacts 4 are controlled in a different manner. If the source and drain contact 3 are actuated at the same time via a common gate contact 42, an ambipolar characteristic is generated, as in a normal FET with a Schottky barrier. Using the gate contact 41 in the center, i.e., between the source contact and drain contact, the RFET is programmed, i.e., the undesired charge carriers in the center of the channel 5 are blocked by the applied voltage on this gate contact 41 (FIG. 3c).
The three cases described show how the polarity of the RFET can be changed by means of an additional programming gate, i.e., by means of the applied voltage on the program gate contact, a unipolar n- or p-type behavior can be programmed dynamically. Thus, the RFET can be operated both as an n- and also as a p-FET. This means that the reconfigurable nanowire transistors combine the electrical properties of unipolar n- and p-type field effect transistors in a single component, wherein the nanowire transistors are constructed according to the same technology, geometry and arrangement. Thus, it is not only possible to reduce the technical complexity, but the possibility is also opened for dynamic programming of circuit functions on the device level. This means that a finer reconfiguration of complex functions is possible. This enables a reconfigurability of the circuits and thus a higher functionality with constant number of components.
However, the disadvantage is that the horizontal RFETs take up much space due to the top gates (for example, in case A and B) which are in parallel, so that fewer components per surface can be implemented. A smaller active surface moreover leaves little room for the tolerance of some process steps, for example, the silicidation of the wires. In the field of nanotechnology, silicidation is understood to mean the sintering of a metal layer, for example, tungsten, titanium, tantalum or nickel, into a silicon substrate. In the silicidation, for example, with nickel, the nickel reacts by rapid thermal annealing, for example, at a temperature of 500° C., to the silicon, wherein the nickel penetrates into the silicon.
Therefore, the aim of the present invention is to overcome the above-mentioned disadvantages and make an improvement, wherein CMOS circuits with enhanced functionality are to be implemented, and a more compact design is to be achieved.